The present invention relates to a sweep circuit of a key matrix having keys arranged in a matrix form.
Among electronic equipment using LSIs (Large Scale Integrated Circuits), a handheld calculator frequently uses a solar battery cell as a power supply. In an LSI using a solar battery cell as a power supply, the power supply voltage abruptly decreases with an increase in the operating current. Accordingly, power consumption must be as low as possible. In equipment such as a handheld calculator which has operation keys, variations in power consumption upon successive depression of keys present a problem. FIG. 1 is a block diagram showing an example of a hand held calculator using a one-chip LSI having functions of key scanning, arithmetic operations, data entry, and display. Referring to FIG. 1, input and output lines of key scanning of an LSI 1 are connected to a key matrix 2 so as to detect the key operation. A display device 3 comprising a liquid crystal display device receives a digit select signal 4 and a segment select signal 5 for performing dynamic drive. A solar battery cell 6 is connected between power supply terminals Vdd and Vss of the LSI 1. The LSI 1 scans the key matrix 2 so as to detect a depressed key. In order to reduce the number of input and output terminals of key scanning signals, some of the terminals serve both as input and output terminals. In the key matrix 2, a plurality of keys K.sub.11 to K.sub.62 are connected in a matrix form. Output terminals T.sub.1, T.sub.2 and T.sub.3, input/output terminals T.sub.4, T.sub.5 and T.sub.6, and input terminals T.sub.7 and T.sub.8 of the LSI 1 are connected to the key matrix 2. The input/output terminals T.sub.4, T.sub.5 and T.sub.6 are used as input or output terminals by time division. This allows scanning of a larger number of keys with a smaller number of terminals so as to allow ready detection of a depressed key.
The LSI 1 has three output circuits of the same structure which are provided for the output terminals T.sub.1, T.sub.2 and T.sub.3 and output scanning signals through the output terminals T.sub.1, T.sub.2 and T.sub.3. Further, the LSI 1 has three input/output circuits of the same structure which are provided for the input/output terminals T.sub.4, T.sub.5 and T.sub.6, respectively, and receive and output scanning signals through these terminals T.sub.4, T.sub.5 and T.sub.6. Still further, the LSI 1 has two input circuits of the same structure, which receive scanning signals through the input terminals T.sub.7 and T.sub.8.
Each output circuit, each input/output circuit and each input circuit of the LSI comprising metal insulator semiconductor FETs will now be described with reference to FIGS. 2, 3 and 5.
FIG. 2 shows the output circuit provided for the output terminal T.sub.2. In FIG. 2, the elements of this output circuit are designated by numerals with subscript "2" which denotes the output terminal T.sub.2. Referring to FIG. 2, the source of a p-channel transistor 7.sub.2 is connected to a power supply Vdd, and a drain thereof is connected to an output terminals T.sub.2. The drain of an n-channel transistor 9.sub.2 is connected to the output terminals T.sub.2, and the source thereof is connected to a reference potential (grounded). The gates of the p- and n-channel transistors 7.sub.2 and 9.sub.2 are commonly connected to receive a timing pulse D.sub.2 and to produce a scanning signal of "H" level on T.sub.2 during the "L" level period of the timing pulse D.sub.2. Nonoverlapping pulses D.sub.1, D.sub.2 and D.sub.3 are supplied from an internal circuit (not shown) to the gates of transistors 7, 9.
FIG. 3 illustrates the input/output circuit provided for the input/output terminals T.sub.6. In FIG. 3, the elements of the input/output circuit are designated by numerals with a subscript "6" which denotes the input/output terminal T.sub.6. The source of a p-channel transistor 10.sub.6 is connected to the power supply Vdd, and the drain thereof is connected to a input/output terminal T.sub.6. The drain of an n-channel transistor 12.sub.6 is connected to a input/output terminal T.sub.6, and the source thereof is connected to the reference potential. The gates of the p- and n-channel transistors 10.sub.6 and 12.sub.6 are commonly connected to receive a timing pulse D.sub.6. One input terminal of an AND gate 13.sub.6 is connected to a input/output terminal T.sub.6, and the other input terminal receives an inhibit signal INH.sub.6. The AND gate 13.sub.6 produces as a detection signal SK.sub.6 a signal of a level supplied to a input/output terminal T.sub.6 only during the period in which the inhibit signal INH.sub.6 is at "H" level. Nonoverlapping timing pulses D.sub.4, D.sub.5 and D.sub.6 are supplied from an internal circuit (not shown) to the gates of transistors 10, 12. Similarly, just as the scanning signals are produced from the input/output terminals T4, T5 and T6, inhibit signals INH.sub.4, INH.sub.5 and INH.sub.6 supplied thereto are set at "L" level to inhibit input during scanning cycle.
FIG. 4 shows the input circuit provided for the input terminal T.sub.8. In FIG. 4, the elements of this input circuit are designated by numerals with a subscript "8". Referring FIG. 4, the drain of an n-channel transistor 14.sub.8 is connected to a input terminal T.sub.8 to obtain a detection signal SK.sub.8, the source thereof is connected to a reference potential, and the gate thereof is connected to a power supply Vdd.
The potentials at the terminals T.sub.1 to T.sub.6 change as the timing pulses D.sub.1 to D.sub.6 which do not overlap in a period A of the timing chart shown in FIG. 5.
When the key K.sub.23 is operated, its contacts close and a circuit between the output terminal T.sub.2 and the input/output terminal T.sub.6 is formed, as in a period B in FIG. 5. Then, scanning signals corresponding to the timing pulses D.sub.2 and D.sub.6 are supplied as superimposed to the terminal T.sub.6. A detection signal SK.sub.6 of the terminal T.sub.6 is a signal portion corresponding to the timing pulse D.sub.2 and a signal portion corresponding to the timing pulse D.sub.6 is inhibited by the inhibit signal INH.sub.6 and is not supplied to a key processing circuit (not shown) of a later stage connected to the LSI 1. Each schaning cycle starts when timing pulse D.sub.1 is output and ends when the next timing pulse D.sub.1 is output.
When the input/output circuits connected to the input/output terminals T.sub.4, T.sub.5 and T.sub.6 produce scanning signals, the AND gate 13 is closed. It remains closed during the rest of scanning cycle to inhibit output of detection signals SK.sub.4, SK.sub.5 and SK.sub.6. Therefore, the LSI 1 recognizes the signal corresponding to the timing pulse D.sub.2 supplied as the detection signal SK.sub.6 and performs processing corresponding to the operation of the key K.sub.23.
In order to perform this operation, ON resistances R(7) and R(10) of the p-channel transistors 7 and 10 must be set to be sufficiently smaller than those R(9), R(12) and R(14) of the n-channel transistors 9, 12 and 14, and the level of the scanning signal must be changed to draw sufficiently near the voltage of the power supply Vdd. When a key is operated, a DC current path is formed between the short-circuited key terminals. The value of the current flowing in this path is determined by the ON resistances R(9), R(12) and R(14) of the n-channel transistors 9, 12 and 14. Since the n-channel transistors 9, 12 and 14 operate in the saturation range upon depression of a key, the following relation is obtained: EQU R(N).varies.1/(Vdd-Vth).sup.2
where R(N) is the ON resistance of the n-channel transistor;
Vdd is the power supply voltage; and
Vth is the threshold voltage of the n-channel transistor.
Thus, the value of the current flowing in the above-mentioned path significantly changes in accordance with the threshold voltage Vth of the n-channel transistor. When the value of this current increases due to the decrease of the threshold voltage Vth, the power supply voltage of the LSI 1 is lowered and display is obscured or the like if the power supply is a solar battery cell.
A handheld calculator of this arrangement operates, for example, in accordance with the flow chart shown in FIG. 6. In step 1, a discrimination of "Is key depressed?" is performed. If NO, step 1 is repeated. If YES, the flow advances to step 2. In step 2, operation "Judge type of keys" is performed.
Scanning signals are output from the output terminals T.sub.1 to T.sub.3 and input/output terminals T.sub.4 to T.sub.6 during every scanning cycle. Scanning signals are output from the output terminals T.sub.1 to T.sub.3, and input/output terminals T.sub.4 to T.sub.6 during every scanning cycle. Every scanning cycle starts when a timing pulse D.sub.1 is output. When any key is depressed, the scanning signals are supplied through this key to the input/output terminals T.sub.4 to T.sub.6 or input terminals T.sub.7 and T.sub.8. At the same time, detection signals SK.sub.4 to SK.sub.8 are supplied to a key processing circuit 31. The key processing circuit 31 identifies these detection signals, thus detecting the depressed key, in accordance with the period of time which elaspes after the start of the scanning cycle until the receipt of the detection signals, i.e., in accordance with the phase differences between these signals, on the one hand, and the timing pulse D.sub.1, on the other hand. In step 3, "Effect calculation or execute entry data" is performed. In other words, arithmetic operations or data entry are performed in accordance with the type of key discriminated in step 2. When step 3 is completed, a discrimination of " Is key released?" is performed in the next step 4. If the key is released in step 4, the flow returns to step 1 of a routine for waiting for next key to be depressed. If the key is not released in step 4, step 4 is repeated and enters a closed loop for waiting for the depressed key to be released. Since the type of key is discriminated in step 1 or 2 in accordance with the phase of the detection signal SKk (k=4, 5, . . . , 8), the pulse edge of the detection signal SKk must be sufficiently sharp.
In contrast to this, the release of the depressed key need only be discriminated in step 4. Therefore, the discrimination of step 4 can be performed in accordance with the level of the voltage of the scanning signal supplied to the input terminal. However, in the discrimination routine of step 4, if the key is not released, when the scanning signal scans the depressed key, a feed-through current flows from the power supply Vdd to the reference potential through the shortcircuited key to force a high load current to the power supply 6. Such a feed-through current repeatedly flows upon every scanning until the depressed key is finally released, thus consuming most of the total power consumption.